1. Field of the Invention
The present invention relates to packet processing devices and recording media recording a packet processing program, and more particularly, to a packet processing device for receiving a plurality of flows of packets arriving in random order and assembling the packets according to the flows, and a recording medium recording a packet processing program for performing such process.
2. Description of the Related Art
The performance of computers as well as the transmission rates of computer networks have been exponentially improving with the years, while restrictions remain placed on packet sizes in order to maintain compatibility of communication schemes. Interfaces connecting computers and networks are therefore required to handle packets of small sizes, compared to the transmission rate, thus constituting a bottleneck in the communication performance.
In TCP (Transmission Control Protocol)/IP (Internet Protocol) communications over Ethernet (registered trademark), for example, a maximum packet size is normally set at about 1500 bytes. Thus, a 10-gigabit Ethernet network operating at full capacity demands that computers transmit/receive approximately 830,000 packets/second, even though the packet size is at a maximum (about 1500 bytes). Consequently, protocol processes of segmenting data into packets for transmission and acquiring data from received packets constitute an extremely heavy load on the processors of computers.
The situation can be improved by enlarging the packet size. However, enlargement of the packet size requires that computer network devices such as switches should be able to handle such large-sized packets, and thus cannot be applied to existing networks. Conventionally, therefore, a network interface circuit is so configured as to perform the function of segmenting data into a plurality of small-sized packets for transmission, to thereby mitigate the load on the processor of a transmitting-side computer.
The receiving side, on the other hand, receives a large number of flows of packets randomly transmitted from various sources, and since some packets are delayed or lost, the received packets cannot be mechanically processed, unlike at the transmitting side. Accordingly, a packet processing device is provided between a network and a receiving-side computer to assemble received packets into larger-sized packets. FIG. 15 shows the configuration of a conventional packet processing device.
A packet received via a network is sent to a packet queue 901 and a packet parser 902. The packet queue 901 is a buffer for storing packets. The packet parser 902 accumulates flow information (INFO) in a flow table (storage device) 903. The flow information is a combination of packet analysis information, which includes identification information such as IP addresses and port numbers extracted from the header of the packet and position information indicating the packet position on the flow, and management information such as a timer/counter for measuring time up to the arrival of a succeeding packet. A flow processor 904 looks up the flow information stored in the flow table 903 to determine a flow to be assembled, and sends the corresponding flow information to a DMA (Direct Memory Access) engine 905. In accordance with the flow information, the DMA engine 905 assembles the target packets stored in the packet queue 901 and transfers the packets to the memory of a host.
There has also been proposed a packet processing device in which, in accordance with an available buffer size of the higher-layer protocol, lower-layer packets are reassembled into a single big packet (e.g., Unexamined Japanese Patent Publication No. 2000-332817 (cf. paragraph nos. [0067] to [0084], FIG. 4)).
However, the conventional packet processing devices are associated with the problem that it is difficult to effectively assemble packets especially during communication of a large number of flows.
The conventional packet assembling process is managed by the flow table, and in order for received packets to be effectively assembled during communication of numerous flows, the flow table needs to hold a sufficiently large number of entries. Also, in some flow tables, forwarding addresses are linked in a direct manner or by a protocol such as an RDMA protocol, and the number of entries of the flow table restricts the number of flows to be communicated. However, in cases where the host is a server or the like, the number of receive flows is as large as several thousands to several tens of thousands, and from the point of view of hardware capabilities, it is difficult to permit the entry of all flows and to assemble all flows in parallel. Excessively increasing the number of entries of the flow table, on the other hand, entails waste of memory capacity and thus is not desirable.
Further, in order to assemble packets into a big packet, the transfer of packets to the host needs to be delayed to wait for the arrival of succeeding packets. Accordingly, in cases where the packet assembling range is not specified by a protocol like TCP, the assembling process is terminated mostly due to the time-out of a succeeding packet wait state. As a result, packets are not transferred to the host until the assembling process is terminated, giving rise to the problem that the arrival of packets at the host is delayed.